Leaked listings and benchmarks point to a 16‑core Ryzen 9 9950X3D2 with dual 3D V‑Cache (192MB) and an 8‑core Ryzen 7 9850X3D ahead of CES.
• Leaks show Ryzen 9 9950X3D2 with dual 3D V‑Cache totaling ~192MB L3 • Ryzen 7 9850X3D appears as an 8‑core, 96MB L3 part with ~5.6GHz boost • Benchmarks posted to PassMark/Geekbench are early and may be unreliable
Enthusiast/Performance Perspective: Enthusiasts and users focused on raw gaming and cache‑sensitive workloads see a dual‑V‑Cache 9950X3D2 as an impressive engineering step that could raise peak and low‑frame performance in scenarios that use more cache. Skeptical/Value Perspective: Skeptics highlight the high cost and uncertain real‑world gains — arguing that many games remain bound to a single CCD or to other system bottlenecks, so the price/performance may be poor compared with single‑CCD X3D or high‑clock non‑X3D options. Industry/Engineering Perspective: Industry watchers treat the dual‑cache design as a notable technical milestone (stacking X3D beneath each CCD), useful as a bridge toward future architectures, while noting manufacturing cost, TDP and scheduler challenges that AMD must address for the product to be broadly compelling.
Multiple recent leaks and early benchmark entries suggest AMD is preparing two refreshed Zen 5 X3D desktop CPUs: a flagship Ryzen 9 9950X3D2 that reportedly uses 3D V‑Cache on both CCDs for a combined ~192 MB of L3, and a higher‑clocked single‑CCD Ryzen 7 9850X3D with ~96 MB of L3 cache and faster boost clocks (~5.6 GHz). PassMark and Geekbench listings attributed to the 9950X3D2 show single‑ and multi‑thread scores close to existing 16‑core Ryzen 9 models and list boost clocks around 5.6 GHz; similar specification summaries and leak posts describe the 9950X3D2 as a 16‑core/32‑thread part and the 9850X3D as an 8‑core/16‑thread part with a 120 W TDP. These reports also tie the timing of the announcements to the CES window. [1][2][3][5] Context around the leaks highlights both engineering and product‑positioning angles. Several outlets note the dual‑cache design would be AMD’s first implementation of 3D V‑Cache on both CCDs and that stacking the cache beneath (rather than atop) the CCD is part of Zen 5’s approach to keep thermals and frequencies manageable; advocates see this as a technical milestone that could benefit cache‑sensitive workloads. At the same time, early listings show inconsistent power figures — some reporting a 200 W design target while benchmark entries list 170 W — and reviewers/writers caution that synthetic database entries can be faked and that gaming benefits may be limited by how operating systems and games schedule work across CCDs. That means real‑world gains (especially in single‑CCD‑bound gaming workloads) are uncertain until formal reviews. [2][3][5] In conclusion, the story so far is one of plausible but unconfirmed product leaks: several hardware outlets and benchmark records point to the 9950X3D2 and 9850X3D as distinct Ryzen 9000 X3D refresh SKUs with large (or doubled) V‑Cache and higher clocks, but discrepancies in TDP reporting and the synthetic nature of the listings counsel caution. Expect AMD to either confirm or clarify specifications and pricing around CES, and treat current numbers as provisional until vendor samples and full reviews are available. [2][3][1]
Controversy
There are conflicting reports about the 9950X3D2's power draw and final specs: some leaks and early coverage present a 200W design target for the chip, while PassMark listings and another report list it as 170W, raising questions about which figure is final or whether early listings are accurate. [3][2] Additionally, outlets disagree implicitly about expected gaming benefit — some coverage emphasizes the novelty and potential of dual V‑Cache, while others (and AMD’s past comments) warn that adding a second X3D tile may not deliver proportional gaming gains. [5][3]